IBM Blue Lightning: World’s Fastest 386?

One of the OS/2 Museum’s vintage boards is a genuine Made in U.S.A. Alaris Cougar. These boards were produced by IBM for Alaris and are a bit unusual: There’s a small IBM DLC3 processor in plastic package soldered on board, and there’s also a Socket 2 which accepts regular 5-Volt 486DX/SX processors or a Pentium OverDrive. If a standard ceramic-packaged 486 or OverDrive processor is installed, the on-board DLC3 is disabled.

The IBM DLC3, sometimes designated as BL3 and better known as Blue Lightning, has an aluminum heatsink glued on but requires no fan. After 20 years, the information whether it’s the 75MHz or 100 MHz variant has been lost, but the board is stable when the processor runs at 100 MHz (3 x 33 MHz). And incidentally, the OPTi chipset and notably the Adaptec VL-bus IDE controller are quite good performers, often doing better than newer PCI-based 486 systems.

The Blue Lightning CPU is an interesting beast. There is not a whole lot of information about what the processor really is, but it can be pieced together from various scraps of information. Around 1990, IBM needed low-power 32-bit processors with good performance for its portable systems, but no one offered such CPUs yet. IBM licensed the 386SX core from Intel and turned it into the IBM 386SLC processor (SLC reportedly stood for “Super Little Chip”).

Later on, IBM updated the processor to support 486 instructions. It is worth noting that there were still the SLC variants available—nominally a 486, but with a 16-bit bus.

The licensing conditions reportedly prevented IBM from selling the SLC processors on the free market. They were only available in IBM-built systems and always(?) as QFP soldered on a board.

One of the more notable users of the 486SLC and SLC2 processors was IBM’s first ThinkPad laptop series, the 700C (25 MHz SLC, upgradable) and 720C (50 MHz SLC2) from 1992 and 1993, respectively. Blue Lightning processors were also used in some IBM PS/2 desktops.

The Cougar board of course sports a DLC3, i.e. a clock-tripled variant with 32-bit bus. This processor is very interesting: It’s essentially a 386 core, updated to handle 486 instructions (there weren’t too many), and equipped with a whopping 16KB of write-back L1 cache.

The 386-ness of the Blue Lightning is most apparent with regard to FPU architecture. The CPU itself has no built-in coprocessor, and most software recognizes it as a 486SX. However, unlike a 486SX, the Blue Lightning can use a regular 387 coprocessor (with the accompanying poor performance relative to a 486DX).

The Cougar is equipped with a 387 socket right next to the soldered CPU. The board came with a Cyrix FasMath coprocessor… which sadly appears to be fried. When the FPU is inserted, the board doesn’t boot at all. Without the coprocessor it works fine. Another FasMath in OS/2 Museum’s has corroded(?) pins which have a tendency to fall off, but after finding a functioning FPU, the system does work and is usually recognized as a 486DX by software.

Performance

Characterizing the Blue Lightning performance is tricky, as it doesn’t much resemble the standard Intel or AMD 486s. The processor core still largely behaves as a 386, which means that performance per clock cycle isn’t great. The catch is that it’s a 386 which a) runs at up to 100MHz, and b) is equipped with superb L1 cache.

Once again, it’s 16KB of write-back L1 cache. Of the common 486s, only the late-model Intel DX4 processors and AMD’s Am5x86 CPUs had L1 cache that was both 16KB and write-back (there were Intel DX4s with 16K write-through cache, and some AMD CPUs with 8K write-back cache).

This impacts the CPU performance in interesting ways. When comparing a 100 MHz IBM DLC3 to a typical Intel DX4 with write-through cache, two things are immediately apparent. First, the 486 core of a DX4 is noticeably faster at reading from the cache, and achieves about 95MB/s bandwidth, compared to approximately 63MB/s on the DLC3. However, the DLC3 can also write at 63MB/s, while the DX4 massively drops to just 31MB/s. The cache behavior is strongly influenced by the fact that the 486 uses 16-byte cache lines while the DLC3 only uses 4-byte cache lines.

The net result is that the DLC3 performance varied depending on exactly what it was used for. In general, it was slower than a DX4 at the same clock speed, but in certain cases it could be faster. It certainly did achieve 486-class performance and a 100 MHz blue lightning was comparable to or slightly better than a 66 MHz 486DX2.

Another confusing area is floating-point performance. When a 486DLC is compared to a 486SX, it does quite well. It is commonly known that a 486SX cannot be equipped with a stand-alone coprocessor, it can only be replaced by a 486DX with a built-in FPU (whether it’s called 487SX or something else).

There is simply no 486DLC variant with a built-in FPU, but a regular 387 can be added. The downside is that the math performance is then similar to a 386+387, and therefore far below that of a 486DX.

IBM intended the Blue Lightning for the typical desktop or portable user with minimal need for math computation. That covered the vast majority of users, but for math-heavy applications, the DLC3 simply wasn’t suitable.

Remarks

The SLC/DLC processors are not to be confused with IBM’s later 486 DX/DX2/DX4 processors, some of which may have been also marketed under the Blue Lightning brand and were commonly available in ceramic PGA packages. Those CPUs were built under a license from Cyrix and were more or less identical to Cx486 processors available under the Cyrix, Texas Instruments, and ST brands.

The 486DLC chips had an interesting deficiency: Despite having a 32-bit address bus and being able to access more than 16MB memory, the internal cache was limited to the first 16MB (presumably due to short cache line tags, designed for the address-space limited  SLC processors). The MSR specifying cacheable regions then only reserved 8 bits for the number of cacheable 64K blocks above 1MB. This limitation probably had little practical impact at the time, as very few systems with Blue Lightning CPUs would have sported more than 16MB RAM. However, the effect can be observed on the above mentioned Alaris Cougar board when equipped with 20MB RAM or more.

The CPUTYPE utility from Undocumented PC claims that a 100 MHz 486DLC3 runs at 104-105 MHz. This is almost certainly caused by a misconception—the utility expects 486 timings for the DIV instruction, but with a 386 core the DLC3 processor really uses 386 timings. Since the DIV instruction is in fact slightly faster on a 386 (38 vs. 40 clocks for a 32-bit register/register divide), CPUTYPE ends up overestimating the CPU frequency slightly. Some other utilities have similar trouble measuring the clock speed; SYSINFO from Norton Utilities is not one of them.

The Blue Lightning is a very interesting example of an older CPU design that modern manufacturing process is applied to. When Intel initially released the 386 in 1985, they had significant difficulties producing chips that could reliably run at 16 MHz, and on-chip cache was deliberately left out because Intel could not manufacture the die with a cache large enough that it’d make a real impact.

Several years later, IBM was able to add a significant cache and run the processors with clock doubling and tripling at frequencies almost ten times faster than the initial 12 MHz 386s. This brought the old 386 design to a point where it easily outperformed many 486s while keeping the power consumption low.

Finally, it needs to be mentioned that the IBM 386SLC was designed to solve some of the same problems as Intel’s 386SL, although the 386SL was meant to be used in conjunction with the SL chipset which IBM presumably wasn’t too interested in. But the Intel 386SL is a different story.

Documentation

No technical documentation of the 486SLC/DLC processors appears to be available. It did exist, but was likely distributed in printed form only. By the time electronic distribution of processor documentation became standard, the 486DLC was already obsolete. Any pointers to detailed Blue Lightning documentation are welcome.